Details of Award
NERC Reference : NE/N019121/1
Learning how to parallelise code and exploit emerging computing hardware
Training Grant Award
- Lead Supervisor:
- Dr D Topping, The University of Manchester, Earth Atmospheric and Env Sciences
- Grant held at:
- The University of Manchester, Earth Atmospheric and Env Sciences
- Science Area:
- Atmospheric
- Earth
- Freshwater
- Marine
- Terrestrial
- Overall Classification:
- Atmospheric
- ENRIs:
- Biodiversity
- Environmental Risks and Hazards
- Global Change
- Natural Resource Management
- Pollution and Waste
- Science Topics:
- Computer Sys. & Architecture
- Fundamentals of Computing
- New & Emerging Comp. Paradigms
- Parallel Computing
- Abstract:
- A significant proportion of NERC research involves modelling and simulation or data processing and analysis, all undertaken on computational hardware. Traditionally such hardware has increased in speed by accelerating the clock speed of the computer chips. However, hardware vendors have abandoned the increasing clock speed route in favour of parallelism. Whilst parallel computing has been around for some decades, only the last few years have seen multi-core chips as standard in desktops/workstations that NERC scientists will be using daily. Furthermore, other recent hardware development routes have led to co-processors such as Intel's Xeon Phi and GPUs by NVIDIA, AMD and ARM. How do we efficiently exploit such hardware? By using shared memory parallelism such as the directives based OpenMP standard, researchers will be able to reduce the time to solution of models/ data analysis they undertake on their commodity machines. A directives based training will also be applicable to existing RCUK facilities and any future investments in emerging hardware for use in regional and national facilities. The overarching deliverable of the proposed course is to impart self-sustainable and 'forward thinking' parallel programming skill sets into the next generation of NERC researchers via a dynamic training environment with both physical and virtual elements. On completion of the course students will: - understand the principles of parallel programming, and its appropriate application - have a wide-ranging understanding of different approaches to parallel programming. - have the skills to analyse existing code & understand how to exploit potential parallelisation - appreciate how multicore programming can accelerate code and support running models of increasing process complexity in a manageable time-to-solution. It is important to provide a dynamic training environment. For this reason, the course will include a virtual, hands-on and follow up training element. This includes an online set of training materials available to any NERC student, not just those attending the hands on tutorials. For those attending the hands on element, support will be structured around video conferences scheduled for 1 week, 1 month and 2 months after the training, and a set of email exchanges between each participant and the tutors. Each participant will be invited to submit a short Case Study on their improved code. The Case Studies will be published on the training portal, available to all NERC students indefinately. Simple coding examples will be performed on laptops before demonstrating CPU multicore potential via access to ARCHER. This provides a great introduction to harnessing the potential of NERC funded facilities. For using external accelerators, we will provide access to facilities at UoM & some demonstrations via MontBlanc low energy cluster. ARCHER & UoM facilities will be reserved for the entire duration of the course, access provided to UoM facility for 2 weeks to give time to practice examples. For using external accelerators, we will provide access to facilities at UoM & some demonstrations via MontBlanc low energy cluster & Intel XeonPhi testbed. A virtual online course will be made accessible to any NERC student after the hands-on event. The current range of NERC short courses has a clear gap in the provision of upskilling from programming to effective use of parallel architectures. Those provided by Archer and NAG do not cover offloading to emerging accelerators. Recent reports from H2020 and global market research places HPC as one of the key contributors to the Digital Single Market (DSM) strategy but identifies a need for improving Skills and Talent in HPC across Europe. The PI's role in the global modelling community, combined with guidance from industrial partners through close relationship with HighEndCompute consulting, will provide a unique course to ensure future skillsets are beneficial across NERCs remit.
- NERC Reference:
- NE/N019121/1
- Grant Stage:
- Completed
- Scheme:
- Doctoral Training
- Grant Status:
- Closed
- Programme:
- Advanced Training
This training grant award has a total value of £30,227
FDAB - Financial Details (Award breakdown by headings)
| Total - Other Costs |
|---|
| £30,227 |
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